Embodiments of the present invention relate to a non-volatile memory device, and more specifically, to a technology for measuring a read cell current in a non-volatile memory that performs a sensing operation using a current.
Memory devices can be classified as either a volatile memory device or a non-volatile memory device. A non-volatile memory device includes a non-volatile memory cell capable of preserving stored data even when it is not powered. For example, a non-volatile memory device may be implemented as a flash random access memory (flash RAM), a phase change random access memory (PCRAM), or the like.
The PCRAM includes a memory cell that is implemented using a phase change material such as germanium antimony tellurium (GST). If heat is applied to the GST, it changes to a crystalline phase or an amorphous phase, thereby storing data in the memory cell.
A non-volatile memory device (e.g., a magnetic memory, a phase change memory (PCM), or the like) has a data processing speed similar to that of a volatile RAM device. The non-volatile memory device also preserves data even when power is turned off.
FIGS. 1A and 1B illustrate a conventional phase change resistor (PCR) element 4.
Referring to FIGS. 1A and 1B, the PCR element 4 includes a top electrode 1, a bottom electrode 3, and a phase change material (PCM) layer 2 located between the top electrode 1 and the bottom electrode 3. If a voltage and a current are applied to the top electrode 1 and the bottom electrode 3, a current signal is provided to the PCM layer 2, and a temperature of the PCM layer rises, such that an electrical conductive status of the PCM layer 2 changes depending on resistance variation. In this case, the PCM layer 2 may be generally formed of AgInSbTe. The PCM layer 2 uses chalcogenide, main components of which are chalcogen elements (e.g., S, Se and Te). In more detail, the PCM layer 2 may be formed of a germanium antimony tellurium alloy (Ge2Sb2Te5) composed of Ge—Sb—Te.
FIGS. 2A and 2B illustrate a phase change principle of the conventional PCR element 4.
Referring to FIG. 2A, if a current less than a threshold value flows in the PCR element 4, the PCM layer 2 has a temperature suitable for a crystalline phase. Therefore, the PCM layer 2 changes to the crystalline phase, which has a low-resistance.
On the other hand, as shown in FIG. 2B, if a current greater than the threshold value flows in the PCR element 4, the PCM layer 2 has a temperature higher than a melting point. Therefore, the PCM layer 2 changes to an amorphous phase, which has a high-resistance.
As described above, the PCR element 4 can store data corresponding to two resistance phases as non-volatile data. For example, if the PCR element 4 has a low-resistance phase set to data ‘1’ and the PCR element 4 has a high-resistance phase set to data ‘0’, the PCR element 4 may store two logic states for data.
In addition, a phase of the PCM layer (i.e., a phase change resistive material) 2 does not change even when the phase change memory device is powered off. This allows the aforementioned data to be stored as non-volatile data.
FIG. 3 illustrates a write operation of a conventional PCR cell.
Referring to FIG. 3, when a current flows between the top electrode 1 and the bottom electrode 3 of the PCR element 4 for a predetermined time, heat is generated. Therefore, the PCM layer 2 changes from a crystalline phase to an amorphous phase in response to the heat applied to the top electrode 1 and the bottom electrode 3.
In this case, assuming that a low current flows in the PCR element 4 for a predetermined time, a crystalline phase is formed by a low-temperature heating state, such that the PCR element 4 serving as a low-resistance element enters a set state. Otherwise, assuming that a high current flows in the PCR element 4 for the predetermined time, an amorphous phase is formed by a high-temperature heating state, such that the PCR element 4 enters a reset status. Thus, a difference between two phases is represented by a variation in electrical resistance.
Accordingly, in order to write the set state during a write operation mode, a low voltage is applied to the PCR element 4 for a long period of time. On the other hand, in order to write the reset state during the write operation mode, a high voltage is applied to the PCR element 4 for a short period of time.
FIG. 4 is a structural diagram illustrating a read path of a conventional phase change memory device.
Referring to FIG. 4, the conventional phase change memory device includes a unit cell C, a column switching unit 10, and a sense amplifier (sense-amp) 11.
In this case, the unit cell C is coupled between a word line WL and a bit line. The column switching unit 10 is coupled between the bit line of the unit cell C and an input/output (I/O) line SIO, so that it is controlled by a column selection signal. The column switching unit 10 is selectively turned on in response to the column selection signal, so that it controls a connection between the bit line and the I/O line SIO.
Only one signal from among a plurality of column selection signals is activated in an active operation mode, so that a unit cell C coupled to a corresponding bit line is selected.
The sense amplifier 11 is coupled to the I/O line SIO, amplifies a sensing current of the unit cell C, and thus outputs a sensing signal SAOUT.
The aforementioned conventional phase change memory device detects a difference in resistance of the unit cell C selected by the column switching unit 10 using a current, and amplifies the detected resistance difference using the sense amplifier 11.
When measuring a current for a read operation mode, the conventional phase change memory device uses a method disclosed in FIG. 5.
Referring to FIG. 5, as can be seen from the sensing signal SAOUT, a read operation is repeated several times. Some points (e.g., points P1, P2 and P3) selected from among the sensing signal SAOUT are established, and the sensing signal SAOUT obtained from the points P1, P2 and P3 are averaged. A read current is measured using the average result.
However, the above-mentioned read current measurement method includes a current sensed in a read state, a current sensed in a standby state, and other current components in the average resultant value. Therefore it is impossible for the aforementioned read current measurement method to accurately measure the read current.